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It
8 BIT SINGLE CHIP MICROCONTROLLER
Preliminary LC87F57C8A
LC87F57C8A
8-Bit Single Chip Microcontroller incorporating 128K-byte FEPROM and 3K-byte RAM on chip.
Overview
The LC87F57C8A is 8-bit single chip microcontroller with the following one-chip features: - CPU : Operable at a minimum bus cycle time of 100ns - On-chip Flash ROM Capacity : 128K bytes (on-board rewritable) - On-chip RAM Capacity : 3K bytes - two high performance 16-bit timer/counters (can be divided into 8 bit timers) - four 8-bit timers with prescalers - timer for use as date/time clock - one synchronous serial I/O port (with automatic block transmit/receive function) - one asynchronous/synchronous serial I/O port - 12-bit PWM x 2 - 12-channel x 8-bit AD converter - high speed 8-bit parallel interface - high speed clock counter - system clock divider - 20-source 10-vectored interrupt system
Features
(1) Read Only Memory (Flash ROM) - single 5V power supply, on-board writeable - block erase in 128 byte units - 131072 x 8 bits (LC87F57C8A) (2) Bus Cycle Time - 100ns (10MHz) Note: Bus cycle time indicates the speed to read ROM.
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1) Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2) Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This product incorporates technology licensed from Silicon Storage Technology Inc. This catalog provides information as of Feb 2002. Specifications and information herein are subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company. System-Business Div. 1-1-1, Sakata Oizumi-Machi, Gunma, JAPAN Ver.1.00 Apr 03 Microcomputer Business Unit T.Kitamura 1/27
LC87F57C8A
(3) Minimum Instruction Cycle Time : 300ns (10MHz) (4) Ports - Input/output ports Input/output programmable for each bit individually Data direction programmable in nibble units - Input ports - PWM output ports - Oscillator pins - Reset pin - Power supply
43 (P1n, P2n, P70 to P73, P8n, PAn, PBn, PCn) 8 (P0n) 2 (XT1, XT2) 2 (PWM0, PWM1) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to 3, VDD1 to 3)
(5) Timer - Timer 0 : 16-bit timer/counter with capture register Mode 0: Two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register Mode 3: 16-bit counter with 16-bit capture register - Timer 1 : PWM/16-bit timer/counter with toggle output Mode 0: 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output) Mode 1: Two 8-bit PWM Mode 2: 16-bit timer/counter (with toggle output) Toggle output is also possible by using the lower order 8 bits. Mode 3: 16 bit timer (with toggle output) The lower order 8 bits can be used as PWM output. - Timer 4: - Timer 5: - Timer 6: - Timer 7: 8-bit timer with 6-bit prescaler 8-bit timer with 6-bit prescaler 8-bit timer with 6-bit prescaler 8-bit timer with 6-bit prescaler
- Base timer 1. Clock for the base timer is selectable from sub-clock (32.768kHz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. There can be five separate interrupt sources. (6) High speed clock counter 1. Maximum of 20MHz possible (when using a 10MHz main clock). 2. Real-time output (7) Serial interface - SIO 0: 8 bit synchronous serial interface 1. LSB first/MSB first-function available 2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 TCYC) 3. Consecutive automatic data communication (1 - 256 bits) - SIO 1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 TCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 - 2048 TCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 TCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
2/27
Ver.1.00
LC87F57C8A
(8) AD converter - 12-channel x 8-bit AD converter (9) PWM - 2 channel x synchronous variable 12 bit PWM (10) Parallel interface - RS, RD , WR , CS0 outputs (polarity can be toggled) - read/write possible in 1 TCYC (11) Remote receiver circuit (share with P73/INT3/T0IN terminal) - Noise rejection function (The filtering time of the noise rejection filter (1TCYC/32 TCYC/128 TCYC) can be switched by program.) (12) Watchdog timer - External RC circuit is required. - Interrupt or system reset is activated when the timer overflows. (13) Interrupts - 20-source and 10-vectored interrupt function: 1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L Interrupt signal
1 00003H INT0 2 0000BH INT1 3 00013H INT2/T0L/INT4 4 0001BH INT3/INT5/Base timer 5 00023H T0H 6 0002BH T1L/T1H 7 00033H SIO0 8 0003BH SIO1 9 00043H ADC/T6/T7 10 0004BH Port 0/T4/T5/PWM0, PWM1 * Priority Level: X > H > L * For equal priority levels, vector with lowest address takes precedence. (14) Subroutine stack levels - A maximum of 1536 levels (set stack inside RAM) (15) Multiplication and division - 16 bits x 8 bits (5 instruction-cycle times) - 24 bits x 16 bits (12 instruction-cycle times) - 16 bits / 8 bits (8 instruction-cycle times) - 24 bits / 16 bits (12 instruction-cycle times) (16) Oscillation circuits - Built-in RC oscillation circuit used for the system clock - CF oscillation circuit used for the system clock - Crystal oscillation circuit used for the system clock - Built-in frequency variable RC oscillation circuit used for the system clock (17) System clock divider - operable on the lowest power consumption - Minimum instruction cycle time (300ns, 600ns, 1.2s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s can be switched by program (when using 10MHz main clock)
Ver.1.00
3/27
LC87F57C8A
4/27
Ver.1.00
LC87F57C8A
(18) Standby function - HALT mode The HALT mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. This operation mode can be released by a system reset or an interrupt request. - HOLD mode The HOLD mode stops program execution and all oscillation circuits: CF, RC and Crystal oscillations. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES) 2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4 INT5. 3. Supply an interrupt condition to Port 0. - X'tal HOLD mode The X'tal HOLD mode stops program execution and all peripheral circuits except for the base timer. The crystal oscillator maintains its state at HOLD mode inception. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES). 2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5 3. Supply an interrupt condition to Port 0. 4. Supply an interrupt condition to the base timer circuit. (19) Shipping form - QIP64E - SQFP64 (20) Development tools - Evaluation (EVA) chip : LC876093 - Emulator : EVA62S + ECB876600A + SUB875700 + POD64QFP or POD64SQFP - Flash ROM writer adapter :W87F50256Q(QIP64E),W87F57256SQ(SQFP64)
Ver.1.00
5/27
LC87F57C8A
Pin Assignment
PA2/CS0#
PA3/WR#
PA4/RD#
PA5/RS
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PB0/D0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN RES# XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P12/SCK0 2 P13/SO1 3 P14/SI1/SB1 4 P15/SCK1 5 P16/T1PWML 6 P17/T1PWMH/BUZ 7 PWM1 8 PWM0 9 VDD2 10 11 12 13 14 15 16 P00 P01 VSS2 P02 P03/AN3 P04/AN4 P05/AN5 32 31 30 29 28 27 PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN P07/AN7 P06/AN6
PB1/D1 26 25 24 23 22 21 20 19 18 17
VDD3
LC87F5700A QIP64E SQFP64
6/27
VSS3
Ver.1.00
LC87F57C8A
QIP /SQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NAME P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2
QIP /SQFP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
NAME PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA2/CS0# PA3/WR# PA4/RD# PA5/RS P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN RES# XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0
Ver.1.00
7/27
LC87F57C8A
System Block Diagram
Interrupt Control
IR
PLA
Flash ROM Standby Control CF RC Xtal MRC SIO0 Bus Interface ACC Clock Generator PC
SIO1
Port 0
B Register
Timer 0
Port 1
C Register
Timer 1
Port 7 ALU
Timer 4
Port 8
Timer 5
ADC
PSW
PWM0
INT0-3 Noise Rejection Filter Port 2 INT4,,5
RAR
PWM1
RAM
Base Timer
Timer 6
Parallel interface Port A Port B Port C
Stack Pointer
Watch Dog Timer Timer 7
8/27
Ver.1.00
LC87F57C8A
Pin Description
Name VSS1, VSS2 VSS3 VDD1, VDD2 VDD3 Port 0 P00 - P07 I/O I/O Function description Power terminal (-) Power terminal (+) * 8-bit input/output port * Data direction programmable in nibble units * Pull-up resistor provided/not provided (specified in nibble units) * HOLD release input * Port 0 interrupt input * AD converter input port : AN3 (P03)- AN7 (P07) *8-bit input/output port * Data direction programmable for each bit individually * Pull-up resistor provided/not provided (specified by bit) * Other functions P10: SIO0 data output P11: SIO0 data input, bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input, bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output * 8-bit input/output port * Data direction programmable for each bit individually * Pull-up resistor provided/not provided (specified by bit) * Other functions P20-P23: INT4 input/HOLD release input/Timer 1 event input/Timer 0L capture input/Timer 0H capture input P24-P27: NT5 input/HOLD release input/Timer 1 event input/Timer 0L capture input/Timer 0H capture input * Interrupt detection style Rising INT4 INT5 Port 7 P70 - P73 I/O enable enable Option No No Yes
Port 1 P10 - P17
I/O
Yes
Port 2 P20 - P27
I/O
Yes
Falling enable enable
Rising/ falling enable enable
H level disable disable
L level disable disable No
* 4-bit input/output port * Data direction programmable for each bit individually * Pull-up resistor provided/not provided (specified by bit) * Other functions P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer P71: INT1 input/HOLD release input/Timer 0H capture input P72: INT2 input/HOLD release input/Timer 0 event input/Timer0L capture input P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input * Interrupt detection style Rising Falling INT0 INT1 INT2 INT3 enable enable enable enable enable enable enable enable
Rising/ falling disable disable enable enable
H level enable enable disable disable
L level enable enable disable disable
* AD converter input port : AN8 (P70), AN9 (P71)
(Continued)
Ver.1.00
9/27
LC87F57C8A
Name Port 8 P80 - P82
I/O I/O
Function description * 3-bit input/output port * Data direction programmable for each bit individually * Other functions P80-P82 : AD converter input port * 4-bit input/output port * Data direction programmable for each bit individually * Pull-up resistor provided/not provided (specified by bit) * Other functions PA2: Parallel interface output CS0 PA3: Parallel interface output WR PA4: Parallel interface output RD PA5: Parallel interface output RS * 8-bit input/output port * Data direction programmable for each bit individually * Pull-up resistor provided/not provided (specified by bit) * Other functions PB0-PB7 : Parallel interface data input/output, address output * 8-bit input/output port * Data direction programmable for each bit individually * Pull-up resistor provided/not provided (specified by bit) * Other functions PC0-PC7 : Parallel interface address output PWM0 output port PWM1 output port Reset terminal * Input terminal for 32.768kHz X'tal oscillation * Other function AN10 : AD converter input port General input port When not in use, connect terminal to VDD1. * Output terminal for 32.768kHz X'tal oscillation * Other function AN11 : AD converter input port General input port When not in use, set as oscillation and leave terminal open Input terminal for ceramic resonator Output terminal for ceramic resonator
Option No
Port A PA2 - PA5
I/O
Yes
Port B PB0 - PB7
I/O
Yes
Port C PC0 - PC7
I/O
Yes
PWM0 PWM1 RES XT1
O O I I
No No No No
XT2
I/O
No
CF1 CF2
I O
No No
10/27
Ver.1.00
LC87F57C8A
Port Output Configuration
Output configuration and pull-up resistor options are shown in the following table. Input is possible even when a port is in output mode.
Terminal P00 - P07 P10 - P17 P20 - P27 PA2 - PA5 PB0 - PB7(*) PC0 - PC7 P70 P71 - P73 P80 - P82 PWM0, PWM1 XT1 XT2 Option applies to: each bit each bit each bit Option 1 2 1 2 1 2 None None None None None None CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Input only Output for 32.768kHz crystal oscillation Output Format Pull-up resistor Programmable (Note 1) None Programmable Programmable Programmable Programmable Programmable Programmable None None None None
-
Note 1 Programmable pull-up resistor of Port 0 is specified in nibble units (P00 - P03, P04 - P07). (*) When in parallel interface mode, PB0 - PB7 output format is CMOS, regardless of any selected option. Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded.
Example 1 : During backup in hold mode, port output `H' level is supplied from the back-up capacitor.
LSI Power Supply
Back-up capacitor
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Ver.1.00
11/27
LC87F57C8A
Example 2 : During backup in hold mode, output is not held high and its value in unsettled.
LSI Power Supply
Back-up capacitor
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
12/27
Ver.1.00
LC87F57C8A
1. Absolute maximum ratings / Ta=25C, VSS1=VSS2=VSS3=0V
Parameter Supply voltage Input voltage Output voltage Input/Output voltage Symbol VDDMAX VI(1) VO(1) VIO(1) Pins VDD1, VDD2, VDD3 XT1, XT2, CF1 PWM0, PWM1 * Ports 0, 1, 2 * Ports 7, 8 * Ports A, B, C * PWM0, PWM1 * Ports 0, 1, 2 * Ports A, B, C * PWM0, PWM1 P71-P73 P71-P73 * Port 1 * PWM0, PWM1 Port 0 Ports B,2 Ports A, C * P02-P07 * Ports 1, 2 * Ports A, B, C * PWM0, PWM1 P00, P01 Ports 7, 8 Port 7 Port 8 * Port 1 * PWM0, PWM1 Port 0 Ports B,2 Ports A, C QIP64E SQFP64 Conditions VDD1=VDD2 =VDD3 VDD[V] Limits min. typ. -0.3 -0.3 -0.3 -0.3 max. +6.5
VDD+0.3 VDD+0.3 VDD+0.3
unit V
High level output current
Peak output current Total output current
IOPH(1)
* CMOS output * For each pin. For each pin. Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins For each pin.
-10
mA
IOPH(2) IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOPL(1)
-5 -5 -30 -20 -20 -20 20
Low level output current
Peak output current
Total output current
IOPL(2) IOPL(3) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) Pdmax Topg Tstg
For each pin. For each pin. Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Ta= -20 to +70C -20 -55
30 5 15 15 50 70 40 40 429 271 70 125
Maximum power consumption Operating temperature range Storage temperature range
mW C
Ver.1.00
13/27
LC87F57C8A
2. Recommended operating range / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Parameter Operating supply voltage range HOLD voltage Input high voltage Symbol VDD(1) Pins VDD1=VDD2 =VDD3 Conditions 0.294s tCYC 200s 0.588s tCYC 200s Except for on-board rewriting RAM and register data are kept in HOLD mode. 2.5 - 5.5 VDD[V] Limits min. 4.5 2.5 typ. max. 5.5 5.5 unit V
VHD VIH(1)
VIH(2) VIH(3) VIH(4) Input low voltage VIL(1)
VIL(2) VIL(5) VIL(6) Operation cycle time External system clock frequency tCYC
VDD1=VDD2 =VDD3 * Ports 1, 2 * P71-P73 * P70 port input /interrupt * Ports 0, 8 * Ports A, B, C Port 70 Watchdog timer XT1, XT2, CF1, RES * Ports 1, 2 * P71-P73 * P70 port input /interrupt * Ports 0, 8 * Ports A, B, C Port 70 Watchdog Timer XT1, XT2, CF1, RES
2.0
0.3VDD +0.7
5.5 VDD
2.5 - 5.5 2.5 - 5.5
0.3VDD +0.7
VDD VDD VDD
0.1VDD +0.4
0.9VDD
2.5 - 5.5 0.75VDD 2.5 - 5.5 VSS
2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 4.5 - 5.5 2.5 - 5.5 4.5 - 5.5
VSS VSS VSS 0.294 0.588 0.1
0.15VDD +0.4
0.8VDD -1.0
0.25VDD
FEXCF(1)
CF1
Except for on-board rewriting * Leave CF2 pin open * System clock divider set to 1/1 * External clock DUTY=505% * Leave CF2 pin open * System clock divider set to 1/1 * External clock DUTY=505% * Leave CF2 pin open * System clock divider set to 1/2 * Leave CF2 pin open * System clock divider set to 1/2
200 200 10
s
MHz
2.5 - 5.5
0.1
5
4.5 - 5.5
0.2
20.4
2.5 - 5.5
0.1
10
14/27
Ver.1.00
LC87F57C8A
Limits typ. max 10
Parameter Oscillation frequency Range (Note1)
Symbol FmCF(1)
Pins CF1, CF2
Conditions 10MHz ceramic resonator oscillation Refer to figure 1 5MHz ceramic resonator oscillation Refer to figure 1 RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal resonator oscillation Refer to figure 2
VDD[V] 4.5- 5.5
min.
unit MHz
FmCF(2)
CF1, CF2
2.5 - 5.5
5
FmRC FmMRC
2.5 - 5.5 2.5 - 5.5
0.3
1.0 50
2.0
FsX'tal
XT1, XT2
2.5 - 5.5
32.7 68
kHz
(Note 1) The oscillation parameters are shown on Tables 1 and 2. (Note 2) VDD4.5V is required for on-board flash ROM rewriting.
Ver.1.00
15/27
LC87F57C8A
3. Electrical characteristics / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Parameter Input high current Symbol IIH(1) Pins * Ports 0, 1, 2 * Ports 7, 8 * Ports A, B, C * RES * PWM0, PWM1 XT1, XT2 CF1 * Ports 0, 1, 2 * Ports 7, 8 * Ports A, B, C * RES * PWM0, PWM1 XT1, XT2 CF1 * Ports 0, 1, 2 * Ports B, C * PWM0, PWM1 Port A P71-P73 * Ports 0, 1, 2 * Ports B, C * PWM0, PWM1 Conditions * Output disable * Pull-up resistor OFF * VIN=VDD (including the off-leak current of the output Tr.) * Using as an input port * VIN=VDD VIN=VDD * Output disable * Pull-up resistor OFF * VIN=VSS (including the off-leak current of the output Tr.) * Using as an input port * VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-5.0mA IOH=-0.4mA IOH=-0.4mA IOL=10mA IOL=1.6mA IOL=1mA P00, P01 Ports 7, 8 IOL=30mA IOL=1mA VDD[V] 2.5 - 5.5 Limits min. typ. max. 1 unit A
IIH(2) IIH(3) Input low current IIL(1)
2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 -1
1 15
IIL(2) IIL(3) Output high voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistor Hysteresis voltage Rpu
2.5 - 5.5 2.5 - 5.5 4.5 - 5.5 2.5 - 5.5 4.5 - 5.5 2.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 2.5 - 5.5 4.5 - 5.5 2.5 - 5.5
-1 -15 VDD-1
VDD-0.5
V
VDD-1
VDD-0.5
VDD-1 1.5 0.4 0.4 1.5 0.4 V
Output low voltage
Port A
IOL=15mA IOL=2mA
4.5 - 5.5 2.5 - 5.5 2.5 - 5.5 15 40
1.5 0.4 70 k
* Ports 0, 1, 2 * Port 7 * Ports A, B, C * RES * Port 1 * Port 2 * Port 7 All pins
VOH=0.9VDD
VHIS
2.5 - 5.5
0.1VDD
V
Pin capacitance
CP
* All pins except the measured terminal : VIN=VSS * f=1MHz * Ta=25C
2.5 - 5.5
10
pF
16/27
Ver.1.00
LC87F57C8A
4. Serial input/output characteristics / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Parameter Cycle Low level pulse width Symbol tSCK(1) tSCKL(1) tSCKLA(1) Input clock High level pulse width tSCKH(1) tSCKHA(1) Cycle Low level pulse width High level pulse width Cycle Low level pulse width Output clock tSCK(2) tSCKL(2) tSCKH(2) tSCK(3) tSCKL(3) tSCKLA(2) High level pulse width tSCKH(3) tSCKHA(2) Cycle Low level pulse width High level pulse width Data set-up time Data hold time Output delay time tSCK(4) tSCKL(4) tSCKH(4) tsDI SB0(P11), SB1(P14), SI0 SI1 SO0(P10), SO1(P13), SB0(P11), SB1(P14), * Data set-up to SI0CLK * Data hold from SI0CLK * Refer to figure 6 * Data hold from SI0CLK * Time delay from SI0CLK trailing edge to the SO data change in the open drain * Refer to figure 6 2.5 - 5.5 0.03 SCK1(P15) SCK0(P12) SIO0 * CMOS output * Refer to figure 6 SCK0(P12) SIO0 SCK0(P12), * CMOS output * Refer to figure 6 2.5 - 5.5 SCK1(P15) Refer to figure 6 2.5 - 5.5 Pins SCK0(P12) Conditions Refer to figure 6 VDD[V] 2.5 - 5.5 Limits min. 2 1 1 1 3(SIO0) 2 1 1 4/3 1/2 3/4 1/2 2 2.5 - 5.5 2 1/2 1/2 s tCYC
tSCK tSCK
typ.
max.
unit tCYC
Serial input
Serial clock
thDI tdD0
0.03 2.5 - 5.5
1/3tCYC +0.05
Ver.1.00
Serial output
17/27
LC87F57C8A
5. Parallel Input/Output Characteristics / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. Refer to figures 8 and 9 for parallel output timing.
Parameter Symbol Pins Conditions Limits min.
Write cycle, tC(1) Read cycle Address set-up tsA(1) time tsA(2) Address hold time thA(1) thA(2) RS set-up time tsRS(1)
VDD[V] 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5
typ. 1
max.
unit tCYC tCYC & ns
* WR (PA3), PB0-PB7 * RD (PA4), PC0-PC7 RD (PA4), PC0-PC7
RD (PA4), PC0-PC7
From address set-up until control signal changes
1/3tCYC -30ns 2/3tCYC -30ns 1/6tCYC 5 1/6tCYC -15ns 1/6tCYC -15ns 1/3tCYC -15ns 1/3tCYC -15ns 2/3tCYC -15ns 0 1/6tCYC 0 1/6tCYC 0 1/6tCYC -5ns 2/3tCYC -5ns 1/6tCYC -5ns 1/3tCYC -5ns 1/6 tCYC 2/3 tCYC 1/6 tCYC 1/3 tCYC
WR (PA3), PC0-PC7 WR (PA3), RS(PA5), CS (PAX)
From change of RD 2.5 - 5.5 until address change From change of WR 2.5 - 5.5 until address change From change of RS, 2.5 - 5.5 CS until change in
WR
ns tCYC & ns
tsRS(2) tsRS(3)
CS
RD (PA4), RS(PA5) RD (PA4), RS(PA5) RD (PA4), CS (PAX)
from change of RS until change in RD
2.5 - 5.5 2.5 - 5.5
tsCS(1) tsCS(2)
set-up time
From change in until change in WR (PA3), CS (PAX) From change in until change in
WR (PA3), RS(PA5)
CS
RD
2.5 - 5.5 2.5 - 5.5
CS WR
RS hold time
thRS(1) thRS(2) thRS(3)
RD (PA4), RS(PA5),
CS (PAX)
RD (PA4), RS(PA5),
From change in WR 2.5 - 5.5 until change in RS From change in RD 2.5 - 5.5 until change in RS,
CS
ns tCYC & ns ns tCYC & ns ns tCYC & ns
2.5 - 5.5 2.5 - 5.5
CS (PAX) CS
thCS(1) thCS(2)
RD (PA4), RS(PA5)
hold time
WR (PA3), RS(PA5)
From change in RD until change in CS
WR
tWRH(1) WR (PA3) tWRH(2) WR (PA3)
From change in WR 2.5 - 5.5 until change in CS 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5
'H' pulse width
WR
tWRL(1) tWRL(2)
WR (PA3) WR (PA3)
'L' pulse width
(Continued)
18/27
Ver.1.00
LC87F57C8A
Parameter
RD
Symbol tRDH(1) tRDH(2)
Pins
RD (PA4) RD (PA4) RD (PA4) RD (PA4)
Conditions
'H' pulse width
RD
tRDL(1) tRDL(2)
'L' pulse width
Data write tdDT(1) maximum delay tdDT(2) Input data set-up time Input data hold time Output data set-up time
RD (PA4), PB0-PB7 The time delay
Limits VDD[V] min. 2.5 - 5.5 1/6tCYC -5ns 2.5 - 5.5 1/3tCYC -5ns 2.5 - 5.5 1/3tCYC -5ns 2.5 - 5.5 1/2tCYC -5ns 2.5 - 5.5
typ. 1/6 tCYC 1/3 tCYC 1/3 tCYC 1/2 tCYC
max.
unit tCYC & ns
RD (PA4), PB0-PB7
tsDTR(1) RD (PA4), PB0-PB7
thDTR(1) RD (PA4), PB0-PB7
tsDTW(1) RD (PA4), PB0-PB7 tsDTW(2) RD (PA4), PB0-PB7
allowed, from RD leading edge until input data set-up (Note 1) From input data setup to RD leading edge. (Note 2) From RD leading edge until input data hold From output data setup until WR leading edge
1/6tCYC -15ns 1/3tCYC -15ns
2.5 - 5.5 2.5 - 5.5 40
ns
2.5 - 5.5
0
ns
Output data hold time
thDTW(1) RD (PA4), PB0-PB7 From WR leading edge until output data 2.5 - 5.5 thDTW(2) hold
2.5 - 5.5 1/3tCYC -30ns 2.5 - 5.5 1/3tCYC -30ns 2.5 - 5.5 0 0
tCYC & ns
ns
Note 1 : Time until incorrect data of Low disappears. Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1).
6. Pulse input conditions / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins INT0(P70), INT1(P71), INT2(P72) INT4(P20-P23) INT5(P24-P27) INT3(P73) (The noise rejection clock is selected to 1/1.) INT3(P73) (The noise rejection clock is selected to 1/32.) INT3(P73) (The noise rejection clock is selected to 1/128.) RES Conditions * Interrupt acceptable * Timer 0 and 1 event input acceptable * Interrupt acceptable * Timer 0 event input acceptable * Interrupt acceptable * Timer 0 event input acceptable * Interrupt acceptable * Timer 0 event input acceptable Reset acceptable VDD[V ] 2.5 - 5.5 Limits min. typ. 1 max. unit tCYC
tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5)
2.5 - 5.5
2
2.5 - 5.5
64
2.5 - 5.5
256
2.5 - 5.5
200
s
Ver.1.00
19/27
LC87F57C8A
7. AD converter characteristics / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0(P80) - AN2(P82) AN3(P03) - AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) Conditions VDD[V] 3.0 - 5.5 3.0 - 5.5 4.5 - 5.5 3.0 - 5.5 AD conversion time=64 x tCYC (ADCR2=1) (Note 3) 4.5 - 5.5 3.0 - 5.5 VAIN IAINH IAINL VAIN=VDD VAIN=VSS 3.0 - 5.5 3.0 - 5.5 3.0 - 5.5 Limits min. typ. 8 max. 1.5
15.10 (tCYC= 0.588s) 31.36 (tCYC= 0.980s)
(Note 2) AD conversion time=32 x tCYC (ADCR2=0) (Note 3)
unit bit LSB s
97.92
(tCYC= 3.06s)
97.92
(tCYC= 3.06s)
18.82
(tCYC= 0.294s)
97.92
(tCYC= 1.53s)
62.72
(tCYC= 0.980s)
97.92
(tCYC= 1.53s)
Analog input voltage range Analog port input current
VSS
VDD 1
V A
-1
(Note 2) Absolute precision excludes the quantizing error (1/2 LSB). (Note 3) The conversion time is the time from executing the AD conversion instruction to setting the complete digital conversion value in the register.
20/27
Ver.1.00
LC87F57C8A
8. Current dissipation characteristics / Ta=-20C to +70C, VSS1=VSS2=VSS3=0V
Parameter Symbol Pins VDD1 =VDD2 =VDD3 Conditions * FmCF=10MHz by ceramic resonator * FmX'tal=32.768kHz by crystal oscillation * System clock : CF oscillation (10MHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/1 divided * CF1=20MHz by external clock * FmX'tal=32.768kHz by crystal oscillation * System clock : CF1 oscillation (20MHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/2 divided * FmCF=5MHz by ceramic resonator * FmX'tal=32.768kHz by crystal oscillation * System clock : CF oscillation (5MHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/1divided * FmCF=0Hz (when oscillation stops) * FmX'tal=32.768kHz by crystal oscillation * System clock : RC oscillation * frequency variable RC oscillation stops * 1/2 divided * FmCF=0Hz (when oscillation stops) * FmX'al=32.768kHz by crystal oscillation * System clock :1MHz with frequency variable RC oscilatin * Internal RC oscillation stops * 1/2 divided * FmCF=0Hz (when oscillation stops) * FmX'al=32.768kHz by crystal oscillation * System clock : X'tal oscillation (32.768kHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/2 divided VDD[V] 4.5 - 5.5 Limits min. typ. 18 max. 35 unit mA
Current drain during IDDOP(1) basic operation (Note 4)
IDDOP(2)
2.5 - 5.5
19
36
IDDOP(3)
4.5 - 5.5
10
22
IDDOP(4)
2.5 - 4.5
5
15
IDDOP(5)
4.5 - 5.5
2
8
IDDOP(6)
2.5 - 4.5
1
5
IDDOP(7)
4.5 - 5.5
2.5
13
IDDOP(8)
2.5 - 4.5
1.8
9
IDDOP(9)
4.5 - 5.5
50
150
A
IDDOP(10)
2.5 - 4.5
30
120
(Continued)
Ver.1.00
21/27
LC87F57C8A
Parameter Symbol Pins VDD1 =VDD2 =VDD3 Conditions * HALT mode * FmCF=10MHz by ceramic resonator * FmX'tal=32.768kHz by crystal oscillation * System clock : CF oscillation (10MHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/1 divided * HALT mode * CF1=20MHz by external clock * FmX'tal=32.768kHz by crystal oscillation * System clock : CF1 oscillation (20MHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/2 divided * HALT mode * FmCF=5MHz by ceramic resonator * FmX'tal=32.768kHz by crystal oscillation * System clock : CF oscillation (5MHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/1divided * HALT mode * FmCF=0Hz (when oscillation stops) * FmX'tal=32.768kHz by crystal oscillation * System clock : RC oscillation * frequency variable RC oscillation stops * 1/2 divided * HALT mode * FmCF=0Hz (when oscillation stops) * FmX'tal=32.768kHz by crystal oscillation * System clock : 1MHz with frequency variable RC oscilatin * Internal RC oscillation stops * 1/2 divided * HALT mode * FmCF=0Hz (when oscillation stops) * FmX'tal=32.768kHz by crystal oscillation * System clock : X'tal oscillation (32.768kHz) * Internal RC oscillation stops * frequency variable RC oscillation stops * 1/2 divided VDD[V] 4.5 - 5.5 Limits min. typ. 4 max. 10 unit mA
Current drain in IDDHALT(1) HALT mode (Note 4)
IDDHALT(2)
4.5 - 5.5
4.5
14
IDDHALT(3)
4.5 - 5.5
2
5
IDDHALT(4)
2.5 - 4.5
1
3.2
IDDHALT(5)
4.5 - 5.5
0.5
1.5
IDDHALT(6)
2.5 - 4.5
0.3
1
IDDHALT(7)
4.5 - 5.5
1.5
3.6
IDDHALT(8)
2.5 - 4.5
1.3
3.3
IDDHALT(9)
4.5 - 5.5
20
80
A
IDDHALT(10)
2.5 - 4.5
10
50
(Continued)
22/27
Ver.1.00
LC87F57C8A
Parameter Current drain during HOLD mode Current drain during time-base clock HOLD mode Symbol IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 Pins VDD1 Conditions * HOLD mode * CF1=VDD or leave it open (when using external clock) * Time-base clock HOLD mode * CF1=VDD or leave it open (when using external clock) * FmX'tal=32.768kHz by crystal oscillation Limits min. typ. 0.05 0.01 15
VDD[V] 4.5 - 5.5 2.5 - 4.5 4.5 - 5.5
max. 20 15 70
unit A
A
IDDHOLD(4)
2.5 - 4.5
5
40
(Note 4) The current of the output transistors and pull-up MOS transistors are excluded.
9. F-ROM Write Characteristics / Ta=+10C to +55C, VSS1=VSS2=VSS3=0V
Parameter On-board writing current Writing time Symbol IDDFW(1) Pins VDD1 Conditions * 128-byte writing * including erase time current * 128-byte writing * including data erase time * Excluding time to fetch 128 byte data VDD[V] 4.5 - 5.5 Limits min. typ. 30 max. 65 unit mA
tFW(1)
4.5 - 5.5
5.0
10.0
mS
Ver.1.00
23/27
LC87F57C8A
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions: 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator
Frequency Manufacturer Oscillator Recommended circuit Operating parameters supply C1 C2 Rd1 voltage range (15pF) (15pF) 0 0 0 0 4.5 - 5.5V 4.5 - 5.5V 2.5 - 5.5V 2.5 - 5.5V Oscillation stabilizing time typ max 0.03ms 0.03ms 0.03ms 0.03ms 0.30ms 0.30ms 0.30ms 0.30ms Note
10MHz
MURATA
CSLS10M0G53B0
Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2
5MHz
MURATA
CSTCE10M0G52(10pF) (10pF) R0 CSTLS5M00G53(15pF) (15pF) B0 CSTCR5M00G53 (15pF) (15pF) -R0
*The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4)
Subsystem Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions: 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 2. Recommended circuit parameters for the subsystem clock using the crystal oscillation
Frequency Manufacturer Oscillator MC-306 Recommended circuit Parameters C3 C4 Rf Rd2 9pF 9pF OPEN 820k Operating supply voltage range 2.5 - 5.5V Oscillation stabilizing time typ max 1.5s 3s Note
32.768kHz SEIKO EPSON
*The oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a HOLD mode. (Refer to Figure4) (Notes) Since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length.
CF1
CF2 Rd1
XT1
XT2
Rf Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
0.5VDD
Figure 3 AC timing point
24/27
Ver.1.00
LC87F57C8A
VDD Power Supply Reset time RES# VDD limit GND
Internal RC oscillation tmsCF
CF1,CF2 tmsXta
XT1,XT2
Operation mode
Unfixed
Reset
Instruction execution d
Reset time and oscillation stabilizing time
HOLD release signal
HOLD release signal VALID
Internal RC oscillation tmsCF
CF1,CF2 tmsXtal
XT1,XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stabilizing time
Figure 4 Oscillation stabilizing time
Ver.1.00
25/27
LC87F57C8A
VDD RRES
RES
(Note) Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage.
CRES
Figure 5 Reset circuit
SI0CLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
Data RAM transmission period (only SIO0)
DO8
tSCK tSCKL SI0CLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Data RAM transmission period (only SIO0)
tSCKLA SI0CLK: tsDI DATAIN: tdDO DATAOUT: thDI
tSCKHA
Figure 6 Serial input/output test condition
tPIL
tPIH
Figure 7 Pulse input timing condition
26/27
Ver.1.00
LC87F57C8A
*E Parallel input/output timing waveform*F Indirect Setting, Read Mode
tC(1) read cycle ADR/DATA: addr tsA(1)
CS#: tsRS(1) RS: tWRH(1) WR#: tRDH(1) RD#: tdDT(1) DATAin H thDTR(1) data tsDTR(1) tWRL(1) tsRS(2) tRDL(1) thRS(2) thRS(1)
Note: If port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. *E Parallel input/output timing waveform*F Indirect Setting, Write Mode
tC(1) write cycle ADR/DATA: tsA(1) CS#: tsRS(1) RS: tWRH(1) WR#: tWRL(2) RD#: tWRL(1) tsRS(3) tsDTW(1) thRS(1) thRS(3) addr data thDTW(1)
DATAin
Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data.
Figure 8 Indirect mode: Parallel Timing Diagram
Ver.1.00
27/27
LC87F57C8A
*E Parallel input/output timing waveform*F Direct Setting, Read Mode
tC(1) read cycle addr tsA(1) CS#: tsCS(1) DATA: tRDL(2) WR#: tRDH(2) RD#: tdDT(2) DATAin H thDTR(1) data tsDTR(1) thCS(1) thA(1)
ADR:
Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. *E Parallel input/output timing waveform*F Direct Setting, Write Mode
tC(1) write cycle addr tsA(2) CS#: tsCS(2) DATA: data
tsDTW(2) thDTW(2)
ADR:
thA(2)
thCS(2)
WR#: tWRH(2) RD#: tWRL(2)
DATAin:
Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data.
Figure 9 Direct Mode: Parallel input/output Timing Diagrams
28/27
Ver.1.00 (c)2002 SANYO

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